This application claims priority to Great Britain Application No. 0706489.2 filed 3 Apr. 2007, the entire contents of which are hereby incorporated by reference.
1. Field of the Invention
The present invention relates to the field of data processing systems. More particularly, the present invention relates to data processing systems using speculative execution with error recovery mechanisms within instruction processing pipelines.
2. Description of the Prior Art
It is known within systems such as that described in WO-2004/084072 to provide data processing systems with instruction processing pipelines that perform speculative execution based upon processed signal values using the assumption that those signal values are correct and then provide error recovery mechanisms which serve subsequently to detect if the signal values concerned were incorrect and initiate appropriate error recovery actions. These techniques are useful in allowing the data processing system to execute closer to its operational limits (e.g. closer to its maximum clock rate or minimum operating voltage) and thereby achieve improved performance/efficiency whilst maintaining reliability due to the in-built error detection and recovery mechanisms.
A typical error recovery mechanism within these systems for an instruction processing pipeline involves flushing of instructions from the pipeline and reloading the pipeline starting from the erring instruction to try to achieve correct operation. Such pipeline flushing interrupts the normal processing flow and reduces the data processing throughput in a disadvantageous manner. Further advantage can be achieved with the above described techniques if the penalty associated with the occurrence and recovery from an error can be reduced.